With the rapid development of semiconductor manufacturing technologies, semiconductor devices have been developed toward high device density and high integration level. As basic semiconductor devices, transistors have been widely used. With the continuous increase of the device density and the integration level of the semiconductor devices, the critical dimension (CD) of the transistors has become smaller and smaller. To reduce the parasitic capacitance of the gate structure of the transistor and increase the device speed, the gate structure having a high dielectric constant (high-K) dielectric layer and a metal gate (HKMG) has been introduced into the transistor.
However, conventional methods for forming the metal gate on the high-K dielectric layer still face some issues. One of the issues is the mismatch of the work-functions. Because the work-function directly affects the threshold voltage (Vt) and the performance of the device, introducing a work function layer is able to adjust the threshold voltage of the device.
To integrate the semiconductor structures having different threshold voltages, it is desired to form work function layers having the different types and/or different thicknesses on the different regions of a same substrate. One approach is to form different work function layers using patterned mask layers.
However, the precisions of the patterned mask layers are relatively low, it may cause a performance degradation to the semiconductor structure. The disclosed methods and semiconductor structures are directed to solve one or more problems set forth above and other problems in the art.